Image sensors have become ubiquitous. They are widely used in digital still cameras, cellular phones, security cameras, as well as, medical, automobile, and other applications. The technology used to manufacture image sensors, and in particular, complementary metal-oxide-semiconductor (“CMOS”) image sensors (“CIS”), has continued to advance at great pace. For example, the demands of higher resolution and lower power consumption have encouraged the further miniaturization and integration of these image sensors.
FIG. 1 shows a cross-sectional view of a conventional active pixel cell 100 that uses four transistors. This is known in the art as a 4T pixel cell. 4T pixel cell 100 includes a photodiode PD, a transfer transistor T1, a reset transistor T2, a source-follower (“SF”) or amplifier (“AMP”) transistor T3, and a row select (“RS”) transistor T4.
During operation, transfer transistor T1 receives a transfer signal TX, which transfers the charge accumulated in photodiode PD to a floating drain/diffusion node FD. Reset transistor T2 is coupled between a power rail VDD and the node FD to reset the pixel (e.g., discharge or charge the FD and the PD to a preset voltage) under control of a reset signal RST. The node FD is coupled to control the gate of AMP transistor T3. AMP transistor T3 is coupled between the power rail VDD and RS transistor T4. AMP transistor T3 operates as a source-follower providing a high impedance connection to the floating diffusion FD. Finally, RS transistor T4 selectively couples the output of the pixel circuitry to the readout column line under control of a signal RS. Often the photodiode PD of a pixel cell is passivated with a shallow pinning layer to reduce surface defects. In an example where an N type PD is implanted into a P-epitaxial layer, the pinning is formed by a shallow P type implant.
In normal operation, the photodiode PD and node FD are reset to the supply voltage VDD by temporarily asserting the reset signal RST and the transfer signal TX. The image accumulation window (exposure period) is commenced by de-asserting the transfer signal TX and permitting incident light to charge the photodiode PD. As photogenerated electrons accumulate on the photodiode PD, its voltage decreases (electrons are negative charge carriers). The voltage or charge on photodiode PD is indicative of the intensity of the light incident on the photodiode PD during the exposure period. At the end of the exposure period, the reset signal RST is de-asserted to isolate node FD and the transfer signal TX is asserted to couple the photodiode to node FD and hence the gate of AMP transistor T3. The charge transfer causes the voltage of node FD to drop from VDD to a second voltage indicative of the amount of charge (e.g., photogenerated electrons accumulated on the photodiode PD during the exposure period). This second voltage biases AMP transistor T3, which is coupled to the readout column line when the signal RS is asserted on RS transistor T4.
As the pixel-size of CIS become smaller for higher pixel density and lower cost, the active area of the PD has also been reduced. For pinned photodiodes, which are commonly used for CIS, the smaller photodiode area leads to a smaller full-well-capacity (the maximum charge that the PD can hold). The reduced full-well-capacity means lower dynamic range and lower signal-to-noise ratio. Therefore, it is often desirable to increase the full-well-capacity of a pinned photodiode.
In a p-n-p pinned photodiode (illustrated) most commonly used for CIS, a common way to increase the full-well-capacity is to increase the doping level of the N-type PD region by increasing the implantation dosage. However, the N type doping level cannot be too high without causing significant image lag, diode leakage current, and other defect pixels (commonly referred to as white pixels).
Multiple p-n-p-n junctions have been proposed to increase the size of the PD region for charge storage and therefore the full-well-capacity. With optimized implants and layout, a full-well-capacity increase of 50% has been demonstrated without increase in pinning voltage or image lag.
Other techniques for increasing the full-well-capacity have also been suggested. For example, it has been proposed to use solid source diffusion (SSD) or plasma doping to form ultra-shallow junctions. The claimed benefit of these techniques is to reduce the surface P type layer thickness and improve blue sensitivity. Another related technique is to grow epitaxial silicon selectively over the surface of the PD to reduce image lag. While it may be possible that these techniques result in high photodiode capacitance, they also introduce additional thermal fabrication steps that can degrade logic circuit performance. The benefit to increasing the PD full well capacity may be limited because thermal diffusion often leads to long dopant tails and therefore reduced capacitance.
FIGS. 2A through 2D illustrate the conventional process for fabricating a CIS. After the gate layer (e.g., transistors T1-T4) has been formed (FIG. 2A; only the transfer gate is illustrated), the PD region is implanted next to the gate of the transfer transistor T1 (FIG. 2B). After the PD region is implanted, but before the sidewall spacers of the transfer transistors are formed, the pinning layer is implanted (FIG. 2C). This order of fabrication provides pinning under the sidewall spacers, which helps to reduce dark current and white pixels. However, the thermal processing for sidewall spacer formation (FIG. 2D) also causes the P type dopants of the pinning layer to diffuse, resulting in a less abrupt p-n junction and therefore a lower full-well-capacity.